半導体デバイスの特性劣化のパラメータ抽出方法

Extracting method of parameters of deterioration of characteristics of semiconductor device

Abstract

(57)【要約】 【課題】MOSFETのホットキャリアによる損傷分布 を抽出する。 【解決手段】仮想上のデバイスの構造についてのデータ を初期値として入力し、デバイスの損傷の分布のデータ を追加初期値として入力して所定のデバイスシミュレー タによって演算した当該劣化後の仮想のデバイスの電気 特性と、前記デバイスの構造と同等の実際のデバイスを 作成し、所定のストレス状態を印加した後、測定した実 際のデバイスの電気特性とを比較し、一致しない場合 は、前記の追加初期値を変更して前記デバイスシミュレ ータによって当該劣化後の仮想のデバイスの電気特性を 再度演算し、前記比較工程で両者の電気特性がほぼ一致 する場合は、当該追加初期値の損傷の分布を特性劣化の パラメータとして抽出し、一致するまで追加初期値を変 更してデバイスシミュレーションの工程を繰り返す半導 体デバイスの特性劣化のパラメータを抽出する方法。
PROBLEM TO BE SOLVED: To extract parameters of deterioration of characteristics by comparing the electrical characteristics of virtual and actual devices and by executing simulation until the electrical characteristics of the devices are in accord with each other, while changing the distribution of impairment. SOLUTION: Data on a device structure are inputted to and computed by a device simulator, electrical characteristics before deterioration are outputted, an interface level and a trap distribution after the deterioration are inputted as initial values, the value of a charge density ρ and the value of mobility μ at each lattice point are computed, device simulation is executed and the characteristics after the deterioration are outputted (S1-S7). Then, a deterioration rate is calculated from the outputs of the device characteristics before and after the deterioration, a device being equivalent to the initial values is prepared actually, the electrical characteristics of the actual device are measured, an acceleration test is conducted, the electrical characteristics after the deterioration are measured and the deterioration rate of the actual device is calculated (S8-S13). By comparing the deterioration rate obtained by the simulation with that of the actual device (S14) and by obtaining information on the distribution of impairment, accordingly, a design can be made to have an improved predictability. COPYRIGHT: (C)1997,JPO

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Cited By (7)

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    JP-2008225961-ASeptember 25, 2008Sanyo Electric Co Ltd, Sanyo Semiconductor Co Ltd, 三洋半導体株式会社, 三洋電機株式会社Circuit simulation method
    KR-101356425-B1January 28, 2014삼성전자주식회사Method for predicting degradation degree of MOS transistor and circuit character
    US-6291254-B1September 18, 2001Sequence Design, Inc.Methods for determining on-chip interconnect process parameters
    US-6312963-B1November 06, 2001Sequence Design, Inc.Methods for determining on-chip interconnect process parameters
    US-6403389-B1June 11, 2002Sequence Design, Inc.Method for determining on-chip sheet resistivity
    WO-9916107-A2April 01, 1999Frequency Technology, Inc.Methods for determining on-chip interconnect process parameters
    WO-9916107-A3July 29, 1999Frequency Technology IncMethods for determining on-chip interconnect process parameters